The I.sup.2 C bus is a 2-wire bidirectional serial bus for communication between bus devices in a data processing system. Bus devices may include microprocessors, microcontrollers, memory devices, peripheral devices, data converters, and application oriented circuits. Two wires of the I.sup.2 C bus constitute a serial data line (SDA) for communicating data between bus devices, and a serial clock line (SCL) carrying clock signals that control bus access and data transfer.
Each device on the I.sup.2 C bus is identified by a unique address. The least significant bit (LSB) of an address byte constitutes a read/write (R/W) bit that signals whether the current bus transaction is a read operation or a write operation. Of the remaining seven bits, four denote the functional group to which the bus device belongs, leaving three bits which may be freely assigned to form the unique address of the particular bus device. Thus, within a particular device group, or category, eight devices from within the group may reside on a given I.sup.2 C bus.
Many systems use the I.sup.2 C bus to determine the hardware make-up of a system. The various removable components that constitute the system are connected together on the I.sup.2 C bus. Each component contains an I.sup.2 C device that provides information about itself to the system. For example, each device may have a EEPROM module containing vital product data ("VPD") information stored thereon. All of the components in the system are connected on the single I.sup.2 C bus. The system gathers information about the components by polling the various devices on the I.sup.2 C bus. The drawback is that in cases where there is a failure on one of the devices in the system, the failure can potentially cause the entire I.sup.2 C bus to fail (the I.sup.2 C bus will be locked up when the device fails by pulling the SDA and SCL lines of the I.sup.2 C bus to ground). This makes it impossible to isolate the failing device in the system.
Customers increasingly demand that computers be easily serviced, in order to reduce the amount of down-time on the system. It is therefore critical to find a method that allows for better failure isolation in such cases.